/****************************************************************
*   Used for alarm's hour module
****************************************************************/

module alarmCnt24 (
  input   wire        rstn   ,
  input   wire        clk    ,      // when in set mode, use 'set' signal to replace clk
  input   wire        set_alarm,
  input   wire        set    ,

  output  reg  [3:0]  upper  ,      // the ten
  output  reg  [3:0]  low           // the one
);

// low
always @(posedge clk or negedge rstn) begin
  if(~rstn)
    low		<=  4'h0;
  else if(set_alarm) begin
    if((upper == 4'h0 || upper == 4'h1) && low == 4'h9 && set)
      low   <=  4'h0;
		else if(upper == 4'h2 && low == 4'h3 && set)
			low		<= 	4'h0;
    else if(set)
      low   <=  low + 1'b1;
  end
end

// upper
always @(posedge clk or negedge rstn) begin
  if(~rstn) begin
      upper   <=  4'h0;
  end
  else if(set_alarm) begin
    if(upper == 4'h0 && low == 4'h9 && set)
      upper   <=  4'h1;
    else if(upper == 4'h1 && low == 4'h9 && set)
      upper   <=  4'h2;
		else if(upper == 4'h2 && low == 4'h3 && set)
			upper 	<=	4'h0;
  end
end
    
endmodule
